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divFrequencyverilog
- verilog写的任意分频的实现代码，可根据需要配置使用-divide verilog write any implementation code, based on the need to configure
ex1_clkdiv
- Verilog语言编写，通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)