一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.

说明了verilog中如何处理符号数的除法(verilog signed divided)

《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and div