搜索资源列表
ahb2ahb.rar
- AMBA总线AHB TO AHB bridge,AMBA bus AHB TO AHB bridge
ahb_interface.rar
- AHB BUS, Master Slave Arbiter -- example,AHB BUS, Master Slave Arbiter
ACODEH
- AHB总线下的slave ramm的verilog代码 -Verilog code of the AHB bus slave ramm
ahbctrl
- AMBA2.0,ahb总线控制器的实现，来自leon3开源代码-AMBA2.0, the implementation of ahb bus controller, from leon3 open source code
verilog
- AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
AHB
- 基于amba总线协议中的ahb总线的从机模块代码,需要modelsim进行测试仿真(Based on the slave bus module code of AHB bus in AMBA bus protocol, Modelsim is needed to carry out test simulation.)
ahb_sramc
- 基于AHB总线的sram控制器，带有memory bist(SRAM controller based on AHB bus)