搜索资源列表
UnsignMulti
- ALTERA上DE2平台,verilog描述,无符号乘法器,在数码管显示结果。
hex_7seg.rar
- altera DE2开发板上数码管译码的verilog程序,altera DE2 development board Verilog digital tube decoding procedures
CLOCK
- 文通过ALTERA公司的quartus II软件,用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为:计时功能,24小时制计时显示;通过七段数码管动态显示时间;校时设置功能,可分别设置时、分、秒;跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
Altera_Verilog_Coding_Style
- Altera公司的Verilog编程风格 Altera_Verilog_Coding_Style-Altera' s Verilog programming style Altera_Verilog_Coding_Style
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
color_space_converters
- Color space converter in Verilog HDL
lcd2tft
- convert lcd 4 bits to tft 16 bits.Writen verilog,Altera Quartus.
vDDCe
- verilog语言实现的数字下变频设计。在ALTERA的QUUARTUS ii下实现。实用,好用。,已通过测试。 -verilog language digital down-conversion design. Of ALTERA QUUARTUS ii. Practical, easy to use. , Has been tested.
LED
- LED流水灯工作,Altera FPGA控制LED灯,编程使用Verilog语言,控制六个流水灯-6 LEDs,control by FPGA
QuartusII
- 此模块为altera官网提供模块,使用硬件描述语言Verilog语言编写的FFT基于FPGA实现。-This module provides a module for the Altera website, the use of hardware descr iption language Verilog language FFT based on FPGA.
LCD_test
- this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
cordic
- Altera 的CORDIC IP核,Verilog HDL-Altera CORDIC IP core, Verilog HDL
vhdl
- verilog for LVDS altera stratix4
SEG7_LUT
- altera 7-segment verilog code.
I2c_opencores_v13.0
- i2c opencores module for Altera Avalon bus. Verilog.
paobiao
- verilog实现数码跑表,基于ALTERA DE2—70开发板实现验证,其中代码不分模块。-verilog achieve digital stopwatch, to achieve certification based ALTERA DE2-70 development board, regardless of where the code module.
verilog
- 用Verilog实现的各种例程,在altera平台进行测试。(Use Verilog implementation of various routines, in altera platform for testing.)
DDS
- 描述了verilog实现的DDS信号发生器,可以经过FPGA验证,包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证,可以实现信号发生器的基本功能。希望大家珍惜,并好好学习。(Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be
黑金Altera开发板Verilog实例教程
- 控制开发板上的4个LED灯,计数器记到4秒清零,控制LED灯依次亮(Controlling the four leds on the development board, the counter down to the 4 seconds reset, the control the LED light in turn)