搜索资源列表
A9
- clock divider, has multiple versions of clock divider for the de2 board
clock
- 数字时钟led显示，de2开发板，HEX显示分秒-digital clock
LCDtime
- 基于DE2板子上EP4CE115F29C7的用lcd1602显示时钟的VHDL语言，其显示的内容是时分秒，达到23:59:59后全部归零，重新计时。-Based on the DE2 board EP4CE115F29C7 use lcd1602 display clock VHDL language, its display when the content of the minutes, after reaching 23:59:59 all return to zero, the timi
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
clock
- there's a clock divider for DE2 altra board clock (50MHz)