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good20FIFO1_1156903973
- 设计FIFO,使用VERILOG的一篇文章
FIFO
- 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
fifo
- 可综合的Verilog FIFO存储器. This example describes a synthesizable implementation of a FIFO. -Can be integrated Verilog FIFO memory. This example describes a synthesizable implementation of a FIFO.
fifo
- a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
fifo
- fifo 即实现数据的先进先出，是用verilog编写的 就撒开了几分-fifo hjahfjhsjeikkdnakfnakjfakjkf
fifo
- FIFO verilog controller, asyn. circuit
fifo
- 使用verilog语言编写的fifo程序。-Use the fifo verilog language program.
fifo
- 同步fifo的verilog代码，很好的资料，值得学习-Synchronous fifo verilog code, very good information, it is worth learning
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
fifo
- FPGA Verilog语言编写的fifo模块-The fifo module of FPGA Verilog language
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
FIFO--verilog
- 同步jk触发器 实现10进制 简单易懂-jk
FIFO(verilog)
- FIFO 的verilog代码，包含测试源码，可以参考学习FIFO的编写-FIFO written with verilog
Syn_FIFO
- 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
async_fifo
- 异步FIFO verilog 代码 复位到空，读侧以及写侧复位均可以使两侧同时复位，且基本同时放开。-ayschronized FIFO verilog code
uart_fifo_n
- verilog 带fifo的串口收发模块(verilog uart with fifo)