搜索资源列表
sim
- fpga ddr_controller-fpga ddr_controller..................
6713_FPGA
- DSP+FPGA+USB2.0板子电路图 DSP是6713；FPGA是XilinxXC2S200；USB芯片是CY68013A-128AXC-DSP+ FPGA+ USB2.0 circuit board DSP is 6713 FPGA is XilinxXC2S200 USB chip is CY68013A-128AXC
SLC1657
- The Silicore SLC1657 is an eight-bit RISC microcontroller. It is delivered as a VHDL1 soft core2 module, and is intended for use in both ASIC and FPGA type devices. It is useful for microprocessor based embedded control applications such a
PIC10_RISC_Verilog
- The PIC10-compatible microcontroller core was implemented as part of a client project where a small PIC-compatible microprocessor IP Core was needed to be integrated into a CPLD or FPGA. This allowed extremely fast but yet simple firmware programming
AM_VHDL
- AM Demodulator using VHDL for Xilinx FPGA. ISE software
DDSFPGA_cylone
- DDS FPGA 模块，实用，欢迎大家下载-DDS FPGA programmer
61EDA_D195
- FPGA闭环控制电路积分分离式PID算法子程序/算法函数/中断函数 文件列表: 开环.cpp 试电压.cpp 闭环.cpp 闭环PID.cpp 闭环PI打印版.cpp -FPGAPIDPIDPIDPIDFPGAPIDPIDPIDPIDFPGAPIDPIDPIDPIDFPGAPIDPIDPIDPIDFPGAPIDPIDPIDPIDFPGAPIDPIDPIDPIDFPGAPIDPIDPIDPIDFPGAPIDPIDPIDPI
fpganaoz
- 基于FPGA闹钟系统的设计。 1.秒模块实际上是一个计数器，一秒记录一次并输出。 2.分，时模块在一个脉冲上升沿计数一次的基础上，加入了时间调整控制。 3.调整时间的控制模块，在使能信号有效时，才可实现时分的调整。 4.闹钟调整及控制模块，可实现闹钟设时的调节功能。 5.显示模块，实现时间与闹钟显示的切换。 6.闹铃模块，实现闹铃的发声装置。 7.总逻辑模块，实现电子闹钟相应功能的总系统。 -FPGA-based alarm system design. 1. S
FPGA
- Hardware to present opportunities in using FPGA (written for labs)
TemperatureMonitor_lab
- 实现温度的实时的检测，使用Verilog语言，适用于actel公司的FPGA-To achieve real-time temperature detection, the use of Verilog language, the company' s FPGA for actel
vhdl_sram_ctrl
- Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
fpgaserialreadwrite_8.6
- use labview to communicate with fpga
FPGA.Implementations.of.Neural.Networks
- 神经网络的FPGA实现参考，ANN的实时硬件计算越来越受到重视。-Neural network FPGA implementation reference, ANN real-time hardware computing draws more and more attention.
DM5_VGA_img_C5H
- VGA 接口 FPGA实现了，采用显示器显示图片功能-VGA
FPGA
- 清华大学的FPGA培训资料，希望对初学者有一定帮助-Tsinghua University, FPGA training materials, hope to have some help for beginners
CycloneIII
- 有关FPGA的AS、JTAG配置的中文资料-The FPGA-AS, JTAG configuration of the Chinese data
fpga_memory_rev_1_0
- Various memories for Xilinx and Altera FPGA devices. Single-port and Dual-port versions with various numbers of read and write ports. Bundle also includes read-first and write-first varieties with sync and async clocks. All memory compo
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
jj
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采
mentor_pads
- FPGA footprint PCB PCB-FPGA footprint