搜索资源列表
f__adder
- 全加器，半加器，或语句，三个建在一个文件中就可以用了-Full adder, half adder, or statement, three built in one file can be used
testZ
- 八位加法器的原理图实现方法和一位半加器 全加器的原理图实现-Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of
VHDL
- A Full adder using half adder unit in vhdl
sy1_yt
- 在max-plus 环境下使用vhdl语言实现用半加器组成全加器的功能。-In the max-plus environment, using vhdl language component with half adder full adder function.
VHDL
- 加法器、寄存器、半加器、译码器的硬件描述语言的描述-describe summator ，register，half adder,decoder with VHDL
halfadder
- IT IS A VERILOG PROGRAM FOR HALF ADDER.
vhdl_half_adder
- half adder implemented using vhdl. ucf file included
HA_Dataflow_view
- A half-adder adds two 1-bit inputs and produces a sum bit and a carry bit as outputs.
Task1_WithCLK
- half adder with verilog coding for
Task3
- vhdl coding for half adder work with aclk
Half_Adder
- Half adder all styles
06half_adder
- 器件EP4CE6F22C8N 一位半加器(Device EP4CE6F22C8N a half adder)
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
Adder
- VHDL code for 4bit adder and full/half adders
lab0_32
- 大学生专业课的lab，用Verilog实现半加器(the necessary lab for college students to fulfill the function of half-adder)