搜索资源列表
lpm_quick_guide
- altera公司的fpga期间的所有lpm模块的快速设计，涵盖了全部的lpm ip模块-altera during the fpga all lpm module rapid design, cover all the ip module lpm
FPGA.rar
- 利用FPGA的51 IP核实现与单片机和ARM的串口通信,FPGA connect with MCU and ARM
FSK
- 利用FPGA内的IP核来实现FSK，Using FPGA to realize the IP core FSK。-Using FPGA to realize the IP core FSK,
SQRT_IP
- FPGA开发用，开平方的IP核，可供初学者快速上手。-IP
I2C
- IIC通信协议IP核，描述IIC协议在FPGA上的实现-IIC communications protocol IP core
9_fft
- 利用FPGA的IP核来实现fft的设计-The use of FPGA to realize the IP core design fft ,,,,,
PIC10_RISC_Verilog
- The PIC10-compatible microcontroller core was implemented as part of a client project where a small PIC-compatible microprocessor IP Core was needed to be integrated into a CPLD or FPGA. This allowed extremely fast but yet simple firmware programming
I2CSLAVE
- 已经验证过的I2C，slave的IP，core，从一开源网站下载的，代码写的非常好，节省了FPGA的资源，比起以往的slave的CORE，这个CORE减少了寄存器的使用。-Has been verified I2C, slave of the IP, core, from an open source website, the code is written in a very good save FPGA resources than the previous slave of CORE, t
floatmul
- 使用FPGA的IP核实现32位单精度的乘法运算-The use of FPGA-IP core to achieve 32-bit single-precision multiplication
DMA-PCIe
- 利用XILINX的IP核设计DMA传输方式实现电脑和FPGA板之间数据传输文档，很有参考价值。-DMA design by using ips provides by XILINX ,make the communication between PC and FPGA possbile.
Bspii_masttera
- 一种基于CPLD/FPGA的的SPI控制的IP核的实现spi -Based on CPLD/FPGA IP core SPI control realize spi
Embedded_IP_CORE
- fpga开发IP核的资料，值得一看，不错的资料-Embedded_IP_CORE very good
FFT_test
- 在FPGA中实现快速傅立叶变换，调用ALTERA的IP核模块-FFT demo in FPGA
qt
- FPGA软核IP生成工具.保存设置,生成5种常见简单软核,计数器,乘法器,存储器-FPGA-based soft IP core generation tool
uart_io_test
- uart io test,是可用的uart ip,可综合，可用FPGA实现，能直接用于产品-uart io test, is available uart ip, can be integrated, the available FPGA, can be directly used for product
fft512
- 基于verilog IP核的FFT工程，512位FFT运算，(FFT engineering based on Verilog IP kernel and 512 bit FFT operation,)
SPWM信号产生系统IP软核设计及验证
- 针对电力电子领域的需求，采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核．通过数字频率合成技术实现了对电源频率的辅确控制．使电源频率精度达到16位．其中。通过调节控制参数．分别实现了电源频率与载波频率的7级、8级控制．最后。搭建了基于FPGA的测试系统．验证了系统功能的正确性．(According to the requirement of power electronics, the natural sampling method for the design of a full
FSK
- 首先利用IP核记录sin和con波形，然后进行FSK调制，信息为数字信息(Firstly, the IP kernel is used to record the sin and con waveforms, and then the FSK is modulated, and the information is digital information)
FFT v1
- IP core fft verilog code example
divider
- a vhdl code for divide operation in fpga spartan6