FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM

异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory

采用EPM570作为核心，外接FIFO，RAM。可进行数据采集，采用60M时钟的ADC ADS830E。ADC前端电路需要改为差分输入方式以减小电路噪声。该电路经过实际检验可以使用，需要将JTAG电阻改为220以下或者短接。-EPM570 used as a core, external FIFO, RAM. Can be a data collection, using 60M clock ADC ADS830E. ADC front-end circuit differential inpu

此文档为C51单片机串口通讯学习程序（中断+FIFO)-This document is for the C51 microcontroller serial communication learning process (interrupted+ FIFO)