搜索资源列表
ATmega88_cn
- ATmega48/88/168产品特性 • 高性能、低功耗的8 位AVR® 微处理器 – 256/512/512 字节的EEPROM (ATmega48/88/168) 擦写寿命: 100,000 次 – 512/1K/1K 字节的片内SRAM (ATmega48/88/168) – 具有独立振荡器的实时计数器RTC – 六通道PWM – 8路10 位ADC(TQFP 与MLF 封装) – 6路10 位ADC( PDIP 封装) – 可编程的串
SPI)
- 实现主机和从机的通讯，也可实现自受自发的功能。-To achieve master-slave communication
spi.tar
- This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
spi_slave
- SPI slave source code
esclavo4bytes
- source code for a slave SPI
5
- 单片机中的SPI 操作，基于C8051f020-This program accesses a SPI EEPROM using polled mode access. The F02x MCU is configured in 4-wire Single Master Mode, and the EEPROM is the only slave device connected to the SPI bus. The read/write operations are tailored
SPI
- micro spi c++-connect spi mode -master slave
AAT91SAM9260T
- AT91SAM9260引导ADSPBF531(SPI Slave Boot)调试笔记，已通过测试。 -The AT91SAM9260 guide ADSPBF531 (SPI Slave Boot) debugging notes, has been tested.
vspi
- // Serial Peripheral Interface (SPI) // The VSPI core implements an SPI interface compatible with the many // serial EEPROMs, and microcontrollers. The VSPI core is typically used // as an SPI master, but it can be configured as an SPI slave as
arcii_spi_001
- simple spi slave operating in mode 0 in VHDL.
SPI
- verilog slave with simulation mode and file pdf
a51-Spi-with-Slave
- Spi with Slave Mode Example @8051-Spi with Slave Mode Example @8051
C-Spi-with-Slave
- Spi with Slave Mode Example @C
SPI-master-and-slave
- Stm32的SPI主从通讯，两块STM32开发板通讯，通过SPI接口-Stm32 the SPI master and slave communication, two STM32 development board communications, through the SPI interface
SPI-slave-system
- FPGA时序逻辑设计：串行外围设备接口SPI从设备系统，包括串行时钟线SCK，主机输入/从机输出MISO，主机输出/从机输入MOSI和低电平有效的从机选择线SS。环境为Quartus。-FPGA Timing Logic Design: Serial Peripheral Interface SPI Slave Device System Includes Serial Clock Line SCK, Host Input/Slave Output MISO, Host Output/Slave
vSPI-master
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
spi
- 利用VHDL在FPGA内实现SPI总线的主从控制器设计(SPI Master and Slave Controller)
spi_verilog_master_slave_latest.tar
- spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)
STM32F1_I2C_STX-master
- Stm32 spi slave mode with Arduino act as master
STM32F1_I2C_MTX-master
- stm32 will acts as master and Arduino acts as a slave