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VHDLEXAMPLEppt
- 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
C2
- 功能更加完善的基于vhdl的数字时钟设计 有秒表，时钟，时期，闹钟的功能和整点报时，时间调整，日期调整，闹钟的设定 、、、、、、、 秒表有开始，暂停，清零等功能，且只有在暂停的情况下才能清零。
miaobiao 用verilog VHDL描写的秒表程序
- 用verilog VHDL描写的秒表程序，可以显示百分秒，秒和分。-Verilog VHDL with the descr iption of a stopwatch program, can display the arc, seconds and points.
clock
- 电子时钟具有一般时钟所具有的所有功能，定时，报时，显示时间和日期以及秒表等等功能。-electric clock
sheji2
- 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
miaobiao
- 体育用记时秒表，显示MS，S,MIN功能-watch
VHDLforclock
- 用VHDL编写电子时钟芯片，具有整点报时，闹钟，秒表功能，调时可按十分与个位分别调时-The preparation of electronic clock chip with VHDL, with the whole point timekeeping, alarm clock, stopwatch function, can be transferred when the transfer is with a bit difference when the
shuzimiaobiaoVHDL
- 数字秒表的VHDL语言实现，由于系统定时器8253每秒中断18.2次,利用INT 1AH/00H取得中断次数(DX),得到54.945ms的定时单位。 -Digital stopwatch the VHDL language, because the system timer interrupt 18.2 times per second, 8253, made use of INT 1AH/00H interrupt number (DX), by 54.945ms timing uni
A-stopwatch-based-on-FPGA
- 基于FPGA的VHDL语言编写的秒表的源程序，需要在FPGA的平台下进行仿真。-A stopwatch written in VHDL language based on FPGA
miaobiao
- 利用vHdl描述语言实现的60秒秒表。能够实现60秒的计时功能-Use of vHdl descr iption language implementation 60 seconds stopwatch
jishu
- 基于VHDL的计时秒表 59分59秒59 具有计时暂停功能 通过数码管显示-Timing stopwatch 59.59.59 with timing suspended through digital tube display please enter the text to be translated
stopwatch
- VHDL秒表设计，硬件环境为NEXYS4开发板，有暂停功能，7段数码管显示。-VHDL stopwatch design, the hardware environment for the NEXYS4 development board, a pause function, 7 digital tube display.