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- 是一个用 maxplus2做的vhdl 很平常的课程小设计 -is a maxplus2 do with vhdl very common small design courses
CPU_Design
- 基于VHDL的CPU的设计，本科课程设计，实现了一个指令集，能计算加减乘。-CPU design VHDL-based undergraduate curriculum design and implementation of a set of instructions, subtraction, multiplication, can be calculated.
shuzhishizhong
- 数字时钟的verilog程序,课程设计，数字电子技术实验，VHDL-VHDL Verilog.
yu
- 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design