搜索资源列表
desigingCRCwithVDHL
- 用VHDL设计CRC发生器和校验器，供初学者参考。-CRC generator and calibration device for advanced users.
pid
- This includes a PID Controller and a PWN Generator for implementation on an FPGA using VHDL
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
DDS
- 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
bxfsq
- 波形发生器的代码，具有产生正弦波、方波、三角波的功能。-Waveform Generator code has generated sine wave, square, triangle-wave function.
example10
- ：正弦波发生器例程，包括了直接数字频率合成(DDS)的原理以及如何应用CPLD产生频率可控频率的正弦信号。-: Sine wave generator routine, including a direct digital synthesizer (DDS), as well as the application of the principle of frequency control CPLD generated sinusoidal signal frequency.
hamming
- Hamming code generator for 4 bit
Sine
- 正弦波发生器，可以让大家学习正弦多种产生方法，可以设计具体电路-Sine wave generator, allowing them to learn the method for multiple sinusoidal, can design a specific circuit
sheji2
- 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
FFT1024
- System generator code for fft implementation. Pls enjoy it
k_9_rate_1-2_VHDL
- viterbi generator its very good for convolution
vga
- 电视机彩条发生器，有文字，图案等多种选择模式-TV Color Bar Generator, with text, patterns and other selection mode
sha_core
- sha码生成电路，包括测试和仿真环境。 sha码生成电路，包括测试和仿真环境。-sha code generator， include test and simulation scr ipt。
vhdl_code_files
- contains some self generated vhdl files. it includes a clock generator, CRc generator, pulse generator etc.
PWM
- PWM generator made in VHDL
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
vhdl
- 实现信号发生器的vhdl教学代码,提供了串口的功能和发生波形的功能，-Realization of the signal generator vhdl code for teaching
vhdl
- 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
kao_ad71
- EULER numerical analysis method, Verify recognition algorithm based on palmprint recognition undergraduate complete set of online identity, Gaussian white noise generator.
ZufallszahlengeneratorVHDL
- random number generator - 16bit