搜索资源列表
shizhong
- 用vhdl语言描述时钟的功能，并通过七段译码显示输出。-VHDL language used to describe the function of the clock and through the Seven-Segment display decoder output.
EDA
- 地址译码，状态机的编写，三态输出，布司乘法器-Address decoder, the preparation of state machines, three-state output, cloth Division Multiplier
yimaqi
- 7段译码器 将0，1，2，3，4，5，6，7，8，9翻译成数码管显示-7 decoder will be translated into digital 0,1,2,3,4,5,6,7,8,9 display
ee721_project
- has the code of instruction decoder of 8085 .. Not all functions are present only partial code is available.. Comments are welcome
SPhere_Decoder
- Sphere Decoder : an m-file to perform sphere decoding
com_port_decoder
- com port decoder implementation
RS(204.188)design
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po
adpcm-and-ppt
- 包括adpcm的简单讲义 adpcm解码Verilog代码 adpcm编码代码-Including handouts adpcm decoder adpcm simple Verilog code for adpcm coding code
VHDL
- 基于VHDL设计的通用实验CPU中译码器部分，用于进行指令译码。-VHDL design of experiments based on general-purpose CPU in the decoder part, used for instruction decoding.
led
- 七段LED数码显示器是数字系统中常用的数码显示元件，二进制数不能直接在LED数码管上显示，需要用一个BCD七段译码器进行译码。下图给出了一个七段显示译码器的框图及相应的七段LED数码管的示意图。-Seven-segment LED digital display is commonly used in digital systems digital display devices, a binary number can not be directly displayed on the LED
viterbi213
- 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
rlut
- ldpc译码器的部分校验和的原理图转化为VHDL语言。-ldpc decoder part of the checksum of the schematic diagram into VHDL language.
decoder
- 38译码器VHDL语言 可以实现38译码器的功能-38 decoder VHDL language
VHDL
- 加法器、寄存器、半加器、译码器的硬件描述语言的描述-describe summator ，register，half adder,decoder with VHDL
DECODER
- vhdl code for decoder
Seven-Segment-LED-Decoder
- 简单的七段数码管译码器vhdl程序,比较基础,适合初学者练习使用-Simple seven-segment decoder vhdl program basis for comparison, for beginners to use.
VHDL
- 一些简单基本的vhdl代码源程序，包扩三八译码器，数据选择器，30s倒计时器等-Some simple basic VHDL source code procedures, bag expanding 38 decoder, data selector, 30 s down timer, etc
vhdl
- 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
decoder-and-multiplexer
- code vhdl decoder and multiplexer
decoder-2-to-4
- decoder 2 to 4 using vhdl