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VHDL tutor n exam
- verilog hdl. for igginner. tutorial in word file1 KAMPATE
BCH（15,7,2)
- bch（15,7,2）decode and encode in verilog hdl N=15，K=7，T=2时的BCH码编码：
dff-n-d-latch
- Dlatch and D Flipflp code with testbench in Verilog
integrator-n-interpolator
- Integrator and interpolator codes in verilog
jeas_reversable-vedic-multiplier
- reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output