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hex_7seg.rar
- altera DE2开发板上数码管译码的verilog程序,altera DE2 development board Verilog digital tube decoding procedures
DE2_UserManual
- ALTERA公司DE2板子原理图-ALTERA' s DE2 board schematic! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
coded_shift_reg
- this a coded shift register with parallel load on a DE2 Altera design board.-this is a coded shift register with parallel load on a DE2 Altera design board.
LAB2
- 适合初学者的FPGA。Altera de2 板开发试验程序-Suitable for beginners FPGA. Altera de2 board development test program
ADDEE2_NETl
- Altera的DE2开发板上的DM9000A网络FPGA接口及及其驱动driver程序源码，还有 Demo程序源码 -Altera' s DE2 board DM9000A network FPGA interface and its driver driver program source code, as well as the Demo program source code
DE2_Default
- altera DE2 board config files ...do give it a try
ALTERA-DE2
- ALtera公司DE2板子功能介绍和相关实例-Company ALtera DE2 board Features and relevant examples! !
DE2_TV
- 基于fpga的视频处理系统，在Altera的DE2-70开发板上实现。-Fpga-based video processing system, the Altera DE2-70 development board to achieve
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
paobiao
- verilog实现数码跑表，基于ALTERA DE2—70开发板实现验证，其中代码不分模块。-verilog achieve digital stopwatch, to achieve certification based ALTERA DE2-70 development board, regardless of where the code module.