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mxule
- 实现12阶m序列的VHDL，在BASYS2板上测试，平台为Xilinux12，经测试可用，且可修改函数式输出不同阶的m序列-12 order m-sequence of VHDL in the BASYS2 board test platform for Xilinux12 has been tested and available, and can modify the function output sequence of order m
sequence
- 利用Basys2 FPGA 开发板实现简单的序列检测器-Basys2 FPGA development board to achieve a simple sequence detector
Ram_FIFO
- 利用Basys2 FPGA 开发板实现FIFO_ram -Basys2 FPGA development board to achieve FIFO_ram
wave-generator-and-VGA-on-basys2
- 基于BASYS开发板的波形发生器和示波器设计，共有三角波方波锯齿波以及正弦波，最后VGA在显示屏中显示波形。-Waveform generator and oscilloscope design BASYS development board based on a total of sawtooth and square wave triangle wave sine wave finally VGA display in the display.
clock
- 时钟，基于basys2，24小时，显示小时，分钟，秒，有闹钟功能，整点可以报时-Clock, based basys2, 24 hours, hours, minutes, seconds, alarm clock function, the whole point timekeeping can
SNake
- VHDL Source for the basys2 board made a snake that crawls over the 7Seg displays
Frequency
- 实现频率计基于verilog语言，基于basys2板子。数码管显示。外部输入信号。-frequency countting based on verilog
Basys2_rm
- basys2的基本参数，及各引脚功能及设定方法-basys2 of the basic parameters, and each pin functions
VGAPPS2PCORDIC
- FPGA课程设计源码，整合VGA,PS2键盘，CORDIC三角函数算法，在basys2平台上使用完全可行。-FPGA curriculum design source, integrated VGA, PS2 keyboard, CORDIC trigonometric algorithm, used on basys2 platform entirely feasible.
clock_project
- 一款基于basys2的多功能时钟，可以实现闹钟，秒表等功能-Multi functional clock based on basys2
module-song2
- xilinx VERILOG fpga BASYS2 音乐单次播放实现-xilinx VERILOG fpga BASYS2 music single player to achieve
模60计数器
- 基于basys2的模60计数器设计，语言verilog(Design of module 60 counter based on basys2, Language Verilog)
shudiankeshe
- 通过verilog语言编程，通过拨动开关来滚动显示预设的字符(Scroll through the switch to display the preset character by programming in the Verilog language)