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clock2001
- 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
bcd.rar
- vhdl编写的将二进制转BCD码的程序.直接源代码，适合新手编程，语法学习,BCD
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
binary_to_BCD
- 将二进制码转换成BCD码，在verilog环境下可以封装为译码器-BCD code into the binary code in verilog environment is encapsulated as decoder
BCD
- 模为 60 的 BCD码加法计数器，采用verilog语言编写。-BCD code module for the addition of 60 counters, using verilog language.
bin2bcd.v
- FPGA Verilog BIN 2 BCD Conversion code.
bit7_Binary_to_BCD_LED
- 二进制转十进制BCD码 Verilog语言 quartus-Binary to decimal BCD code Verilog language quartusII
b_to_bcd
- Verilog语言编写，二进制码转BCD码-Verilog language, binary code to BCD code
BCDto7seg
- bcd to 7 seg code in verilog
timer_se
- 数字时钟可以显示分、秒，并通过按键进行复位；数字时钟由四个基本模块组成，顶层模块、分频模块、计数模块、译码显示模块。（1）分频模块 分频器将开发板提供的6MHz时钟信号分频得到周期为1s的控制信号，控制计数器改变状态。（2）计数模块：秒钟和分钟利用两个模60的BCD码计数器实现。计数器分为高4位与低4位分别控制低4位每秒钟加1，变化状态为0~9，低4位状态变化到9时，高4位加1，变化状态为0~5。秒钟计数达到59时，分钟低四位从1开始，每59秒加1，低4位状态变化到9时，高4位加1，变化状态为0