搜索资源列表
booth
- -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify
Booth_encoder
- 为提高乘法运算速度本设计采用Booth算法，Booth编码算法的优点有两个：一是减少了部分积的个数；二是可同时适用于有符号数运算和无符号数运算。
zhanhuizhanweiguanlixitong
- 展会展位管理系统。VB+Access开发，提供展会信息的管理系统。-Exhibition booth management system. VB+ Access development, provide fair information management system.
shoppingBusJK_wl
- 这是商店购物系统，在商店里的商品选中的放入购物车，再去售票口。-This is shopping system, the merchandise stores at selected Add to shopping cart, then the ticket booth.
multipilier8x8_spice
- 用spice描述的8x8改进Booth码加wallance压缩的乘法器，并且进行了优化，时间性能相当高-the improved Booth coding plus wallance multipliler ,I have optimized it which gained short time and performance,it is descr ipted by spice
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
MUL
- 8-bit modified Booth s algorithm multiplier
Parallel_Booth_Multiplier
- Parallel Booth Multiplier Circuit in VHDL
booth
- booth multiplier in verilog, deisgn in parameterized.
BOOTH
- booth s substract algorithm
speech
- 文-语转换即Text-to-Speech，简称为TTS，这种技术已经广泛地运用到各种信息查询台、机器人语音等领域中。通过本次实验，了解TTS的基本实现原理，并能在VC++环境中运用TTS技术完成英文的文-语转换。 Windows支持两种RIFF(resource interchange file format,“资源交互文件格式”)音频文件：MIDI的RMID文件和波形音频文件格式Wav文件，而Wav文件是一种经常需要播放获编辑的音频文件，故本实验就要学习设计VC程序完成Wav文件播放的几种
booth
- 布斯公式求补码乘法的算法，用VHDL语言编写-booth algrithm, work out the 2 s complement mulitplier using VHDL
booth
- this implementation of booth multiplier. by this we can implement booth mul in vhdl. we can also implement in verilog.-this is implementation of booth multiplier. by this we can implement booth mul in vhdl. we can also implement in verilog.
booth
- 使用C语言实现 计算机原理中的booth算法 让大家更好的理解-Using C language to realize computer principle, let us better understand the booth algorithm
booth
- 32*32 Booth multiplier
booth.tar
- Booth algorithm multiplier this project design booth multiplier by verilog language. you can open it by ISE and simulate.
第一次实验booth乘法
- mars上运行的booth乘法器，包括报告以及代码(Booth multiplier running on Mars)
booth
- it's booth vhdl code for DE2 altra boards
code
- Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an err
modified_booth_multiplier
- quartus ii项目文件包，功能是改进的booth乘法器，节省时钟，已完成仿真。(This zip file contains a quartus ii project, which can fufill multiple function. It is done by using a modified booth multiplier.)