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haiming
- 信息论与编码中，实现的一个简单的（7,4）系统线性分组码，也即海明码-Construct a systematic (7,4) linear block code.You can use c lauguage or HDL (VHDL or Verilog-HDL) to describe it. Construct a linear block decoder,and decode the received code vector[0 1 0 1 1 0 1].Please write the
ADPCM_ENCODE
- 关于ADPCM编码的verilog程序，很不错，通过了验证。有需要的可以下载-About the verilog ADPCM coding program, very good, verified. if you need，you can to download
IVerrilog_HDDn
- Verilog HDL入门，学习习的最好参考资料，能极短的时间内学会 -Verilog HDL entry, learning the best reference for learning, can be a very short period of time to learn to
Mstateei
- 米勒解码器的状态转换模块。用verilog语言编写写，ISE为开发环境 ，经测试可直接使用。 -Miller decoder state transition module. Verilog language writing, ISE development environment has been tested and can be used directly.
BVerilog_examo
- 关于FPGA的书籍，介绍了大量的Verilog实例例，对初学者很有帮助 ，经测试可直接使用。 -FPGA book introduces the Verilog instance cases, useful for beginners, has been tested and can be used directly.
VSELLLERRe
- 一种基于verilog HDL的自动售货机控制电路设计:能对5种不同种类的货物进行自动售货，价格分别为A=1.00，B=1.50，C=1.80，D=3.10，E=5.00 。售货机能接受1元，5角，111角三种硬币(即有三种输入信号IY，IWJ，IYJ)，并且在一个3位7段LED(二位代表元，一位代表角)显示出来以投入的总钱数，最大9.90元，如果大于该数值，新投入的硬币会退出，选择货物的输入信号I -Verilog HDL-based vending machine control cir
3Code_for_Medx
- 3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。 -3x3 median filter FPGA implementation of the present (VERILOG) can be used directly.
WVerilogHDLi
- 用Verilog HDL语言编写的的跑马灯小程序，可直接在FPGA上运行 -Marquee applet written using Verilog HDL language can be directly run on the FPGA
booth
- this implementation of booth multiplier. by this we can implement booth mul in vhdl. we can also implement in verilog.-this is implementation of booth multiplier. by this we can implement booth mul in vhdl. we can also implement in verilog.
iic_func_module
- 基于verilog的对eeprom的读写，该eeprom是基于I2C的读取，里面对时序的理解比较独特，大家可以自己揣摩-Based verilog read and write to eeprom, the eeprom is based I2C read inside relatively unique understanding of the timing, we can try to figure out
can_acf
- can ctrl sja1000 compatible written in verilog part of the files
hdl
- can ctrl sja1000 compatible written in verilog part of the files
Frequency-meter
- 用Verilog语言编写的频率计，可以精确到1Hz-Frequency counter with the Verilog language, can be accurate to 1Hz
iic_t
- I2C协议的verilog实现，包括配置、读写等操作，只需更改器件地址即可使用。-The I2C protocol verilog implementation, including configuration, read and write operations, simply change the device address can be used.
fftverilog
- 用verilog 写的fft计算的程序，可以作为参考-Use verilog write FFT calculation procedures, can be used as a reference
Utaxis
- 用verilog写的基于cpld的出租车计费器的源源码，需要的参考一下 ，经测试可直接使用。 -Verilog write source based the cpld taxi meter source reference, the test can be used directly.
fVerrilog_Devr
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
FoopencoreP
- 基于FPGA的视觉采集系统的实现现，verilog源码可直接使用。 -Visual acquisition system based on FPGA realization now, verilog source code can be used directly.
verilog_1602
- verilog动态驱动lcd1602，可以往指定地址写入指定数据，且只写入一次，不会重复写入-verilog dynamic driver lcd1602, specify the data can be written to the designated address, and only be written to once, not rewritable
mux16
- 乘法器，verilog语言实现，16位*16位，位数可调，改动相应程序即可。-Multiplier, verilog language to achieve, 16* 16 digit adjustable changes corresponding program can.