搜索资源列表
FIFO_Memory
- VHDL设计——FIFO存储器设计-VHDL design -- FIFO design
buffervhdl
- 电子EDA,VHDL语言设计8位的fifo数据缓冲器的vhdl源程序
fifo源程序
- fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
fifo
- 一个FIFO设计的例子，例子简单，但很经典。 是学好数字设计的好开端。-A FIFO design examples, example of simple, but very classic. Learn digital design is a good start.
TS_sychrous_check
- 该模块主要用于MEPGII TS流同步检测。当连续检测到3个TS包同步时，输出一个同步有效信号，在该同步信号的驱动下，TS包写入FIFO中。该模块对检测TS包的有无及是否同步特别有效，希望对做数字电视的朋友有所帮助。-The module is mainly used for synchronous detection MEPGII TS stream. When detected in three consecutive TS packets simultaneously, the outpu
FIFORAM
- FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
fifo_design
- 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
fifo
- 这是一个用VHDL编写FIFO模块，已经通过测试-fifo
FIFO
- fifo的实现，可以作用于memory的数据传输等地方，在fpga上实现，可以进行综合和仿真-fifo implementation, you can act on memory data transfer and other places, in the fpga to achieve, to undertake a comprehensive and Simulation
FIFO_32B
- This file is the implementation of a 32B FIFO in VHDL and can be implemented as Gate level. It was developed by ISE7.1
sycfifo
- 并行fifo存储器，vhdl语言编写。可设置fifo的宽度和深度。-fifo
FIFO
- vhdl code for first in first out
12345
- 用vhdl编写的带fifo的uart，西电自动化系的作业-The vhdl write uart with fifo
MCTP1
- Vhdl 同步FIFO设计 该FIFO 实现方案比传统方式简单,工作速度频率高-Vhdl synchronous FIFO design of the FIFO implementations simpler than traditional, high working speed frequency
FIFO
- 实现FIFO（先进先出）存储器设计,用VHDL实现 -to implement the FIFO meoney
FIFO_TXD
- fifo标准协议接受代码，基于fpga，vhdl语言-fifo standard protocol accepted code, based on fpga, vhdl language
FIFO
- first input and first output vhdl code
FIFO
- FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
fifo_control
- vivado project file for fifo in vhdl