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AES-based-on-FPGA-jiemi
- 基于FPGA的AES算法实现，使用verilog语言实现。本模块只包含解密过程，没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process.
A-compact-AES-core-with-on-line-error-detection-f
- This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logi
IYUG
- The AES-128 implementation as depicted in Figure 3 has been implemented on the FPGA. This required an initial round key addition followed by ten rounds of S-Box.
ALTERA
- we are in this file about altera fpga xilinx communication syaterm toolbox for design and system requirements
AES加密_解密_verilog代码
- 用Velirog语言实现AES加密解密，可在FPGA上实现(AES encryption and decryption in Velirog language)
基于FPGA的AES256位加密
- aes 256位 算法 加密程序，使用verilog 语言(AES 256 bit algorithm encryption program, using Verilog language)