FPGA控制的AD转换程序,实现读取AD数据功能,并实现与DSP接口功能,FPGA to control the conversion process of AD, AD to read data to achieve functionality and interface with the DSP function

FPGA与DSP数据接口转换时序，简单实用的，SDRAM时序读写数据。-FPGA and DSP data interface conversion timing, simple and practical, SDRAM read and write data timing.

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul

FPGA的I/O接口方向控制的设计，主要应用于与DSP/CPU等接口。-FPGA s I/O interface design direction control, mainly used in the DSP/CPU and other interfaces.