Turbo编码的FPGA实现，采用了（7，5）RSC编码和循环移位交织，帧长度128bit(The FPGA implementation of Turbo coding adopts (7, 5) RSC coding and cyclic shift interleaving, and the frame length is 128bit.)

使用了Sova译码算法，实现的基于FPGA的Turbo码译码算法。( U4F7F u7528 u4B01 u7B1 u7B1 u7B1 u7801 u7B97 u6CD5 uFF0C u5B9E u73B0 u7684 u57FA u4E8EFPGA u7684Turbo u7801 u8BD1 u7801 u7B97 u6CD5 u3002)