搜索资源列表
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
Multi_Cycle_Microprocessor_with_Control
- Multi Cycle processor with control logic Verilog Computer organization and design
Multicycle
- verilog multi cycle. all modules
Verilog
- 用Verilog语言编写的多功能数字钟，用七段显示时钟-Verilog language, multi-function digital clock clock, seven-segment display
mp2
- 用verilog 写的微程序多周期CPU.软件版本为10.1-Micro-program written in verilog. Multi-cycle CPU software version 10.1
multi_cpu
- 用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
shuzizhong
- 基于VeRILOG语言的多功能数字钟，已在FPGA板子上实现-Multi-function digital clock based VeRILOG language has been implemented on the FPGA board
yuandaima
- 以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境-GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II
Multiperiod-microprocessor
- 多周期微处理器设计，verilog，在FPGA上实现，内含实验报告和代码-Multi cycle microprocessor design, Verilog, on the FPGA to achieve, including the experimental report and code
control_s
- 数控机床 多轴插补原理积分算法，实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)
ECOP
- 关于verilog语言的多周期cpu实现的方式(Multi cycle CPU implementation)