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zad6_multiplekser
- Multiplexer in VHDL (Quartus)
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
erxuanyiduoluxuanzeqi_no_maoxian
- 二选一多路选择器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-Choose one multiplexer selector verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
decoder-and-multiplexer
- code vhdl decoder and multiplexer
mux2_1
- Multiplexer using VHDL
mux4to1
- this file is vhdl code od multiplexer 4 bit.it is structral
muxcounter
- Multiplexer styles in VHDL
MUX_do
- a multiplexer in vhdl language