The OP07 has very low input offset voltage (75 μV max for OP07E) which is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current (±4 nA

Noise Generator Schematic using ATmega128 and AD7541 dac , AD9854 dds is added t-Noise Generator Schematic using ATmega128 and AD7541 dac , AD9854 dds is added too...