SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the rati

读SD卡，主要涉及SOPC技术，NIOS软核编程，供学习参考用-Reading SD card, mainly related to SOPC technology, NIOS soft-core programming for the study and reference

AC6901电路板原理图，用于指导以AC6901为核心的包含蓝牙/收音机/USB/SD卡等音频传输播放功能硬件系统开发。(Schematic diagram of AC6901 circuit board to guide the AC6901 as the core, including Bluetooth / radio /USB/ SD card audio transmission function hardware system development)

Ready to use sd card root for simulating an atari st with Mist FPGA computer