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11912930snug06_cohen_sri_aji1.tar
- system verilog 的好例子 system verilog 的好例子
ovm-2.0.2
- OVM(Open Verification Methdology) for system verilog or systemC
systemverilog
- a good book on system verilog
sc2v_latest.tar
- system C to verilog converter
sva
- SVA reference manual-quick system verilog reference manual
vmm-1[1].1.1.tar
- vmm system verilog source code
Automatic_Car_Parking_using_FPGA
- it about automatic car parking system in verilog
traffic
- verilog交通灯程式，分别A方向和B方向的交通灯,-verilog of traffic light system,which are A direction and B direction of traffic light.
LIP1701CORE_system_watchdog
- System watchdog verilog code
VMMing-a-SV
- vmm不错的学习资料，如何搭建testbench，很多实用的例子。推荐初学者。-study vmm of system-verilog
SV_UVM_practice_codes.sv.tar
- system verilog example codes
verilog-system-function
- verilog系统函数的详细讲解并附带例子，对初学者很有帮助-verilog explain in detail and with examples of system functions, useful for beginners
Fpga_control
- FPGA做机器人舵机控制系统，verilog-FPGA to do the robot servo control system, verilog
SVV
- System verilog questions
04_OVM_mechanics
- OVM即开放验证方法（机制篇） 基于system verilog语言-OVM (Open Verification Mechanism) source code. System verilog language
sv_lab_switch
- system verilog ASIC 验证平台编写详细实例-system verilog testbench for ASIC
students-website-in-JSP--Students3k.com
- In this homework, you will need to compile and simulate a System Verilog program . (Constraint_mode_ex.sv) which implements multiple constrained-random test A more detailed descr iption of the program can be found below:
verilog
- AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
Verilog数字系统设计教程
- verilog数字系统设计教程，全面，专业，非常不错，适合初学者(Verilog digital system design course, comprehensive, professional, very good, suitable for beginners.)