搜索资源列表
Altera_uart_Verilog
- FPGA/CPLD应用,uart的Verilog HDL原码-FPGA / CPLD applications, UART Verilog HDL source
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
uart
- FPGA上的verilog 的uart实现方法-FPGA on the verilog uart implementation
uart_ps2
- ps2接口的verilog module 负责用键盘发送数据，附带仿真task仿真，代码简单明了。 uart接口的verilog module ，通过PC机上的串口助手接收并显示键盘发送的数据 FPGA 板调试OK-ps2 verilog module with uart verilog module,fpga simulation ok.ps2 send data and uart get data and display in PC
S8_UART_V2
- 红色飓风开发板提供uart串口程序，verilog实现，一定可以参考并使用-FPGA uart verilog
UART_source_code
- uart verilog code for nexys2 fpga borad
FPAG UART Verilog
- FPGA实现URAT，实现异步串口收发控制(FPGA implements URAT to realize asynchronous serial port and transceiver control)