URISC处理器的VHDL实现,采用模块化思想自顶向下实现，内部自定义总线模块-URISC PROCESSOR

自己用verilog编写的urisc程序，调试成功，压缩包里有仿真图像，值得学习参考。-Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.