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cpu的VERILOG描述
- RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL descr iption
Verilog HDL 语言编程 RS(204,188)译码器的设计
- Verilog HDL 语言编程 RS(204,188)译码器的设计源码
Verilog_Hdl48FIR
- verilog hdl fir 48阶-verilog hdl fir
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
i2s_rel1_2
- I2S verilog HDL code including test environment
cpld11245
- 主要介绍了等精度频率测量原理，该原理具有在整个测试频段内保持高精度频率 测量的优点 同时在该原理基础上，采用了Verilog HDL语言设计了高速的等精度测频 模块，并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人，实现了计数等 主要逻辑功能 还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设 计实现了对频率变化范围较大的信号进行频率测量，能够满足高速度、高精度的测频要 求。-Introduced, such as the accuracy
color_space_converters
- Color space converter in Verilog HDL
traffic
- verilog HDl 交通灯的实现,而且这是有别于一般的vhdl语言-verilog HDl traffic light
IOcontrol
- 输入输出控制的状态机，verilog HDL源码-Input and output control state machine, verilog HDL source
i2c.tar
- I2C verilog HDL code including test environment
Design_and_verification_verilog_hdl
- 设计与验证verilog hdl配套光盘-Design and verification verilog hdl" supporting CD-ROM
4-bit-mictroprocessor-heaving-4-bit-address-space
- 4 bit mictoprocessor in verilog HDL heaving 4 bit address space
mt48lc4m32b2
- SDRAM module Verilog HDL-SDRAM module Verilog HDL
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
verilog
- verilog hdl 交通灯控制实验 源代码为y4.v-verilog hdl traffic light control experiment source code y4.v
Verilog-HDL
- Verilog HDL的基本语法的学习资料。-Verilog HDL the basic syntax.
Verilog-source130
- Verilog HDL 源代码设计 一共有130个例子,欢迎下载-Verilog HDLsource130
cnt12
- 十二进制计数器，基于verilog HDL实现。(Twelve decimal counter)
VERILOG+HDL快速入门
- VERILOG HDL 快速入门(VERILOG Quick Reference Manual)