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LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
Design_and_verification_verilog_hdl
- 设计与验证verilog hdl配套光盘-Design and verification verilog hdl" supporting CD-ROM
RS(204.188)design
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po
GenRomSch
- Rom的二进制文件转换成verilog 文件-Rom bin file changed to verilog file
Pro_19
- Fpga,DDS,PLL,rom(正弦波)(f<13MHz,需要滤波)(Verilog)-Fpga, DDS, PLL, rom
pud_ben
- Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)
cpu_me
- 采用verilog编写的cpu,modelsim仿真均实现8条指令功能，有虚拟ram和rom-Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom