搜索资源列表
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
63535309sram
- verilog编写的读写SRAM的源码，包括sram的读写控制-SRAM read and write verilog source code written in, including the sram to read and write control
DDDRR_SDRAM_cD
- DDR SRAM控制器的verilog完整设设计文档（包含有完整的verilog源代码）， -DDR SRAM controller the verilog complete set design document (contains the complete source code verilog)
verilog_SRAM-test
- verilog 进阶实验_SRAM：SRAM 测试-verilog Advanced experimental _SRAM: SRAM test
SRAM
- sram verilog里面包含了 sram verlog学习之后写的 一些相关程序-is good for sram verilog sdudy
sync_fifo
- Verilog HDL code for synchronous SRAM FIFO
gds8k_32bit_1M
- 一款SRAM的verilog代码及版图信息-verilog codes and layout information of a RAM
bus_ahb_to_sram
- amba ahb to sram verilog
S21_SRAM
- 红色飓风fpga开发板提供sram驱动程序，verilog实现，想学习FPGA同学一定要参考并使用，挺实用-FPGA verilog sram
5SDRAM.tar
- SRAM接口的verilog代码，用verilog编写，片上系统SOC源代码分析的SRAM接口代码，总线是wishbone-SRAM u63A5 u53E3 u7684verilog u4EE3 u7801 uFF0C u7528verilog u7F16 u5199 uFF0C u7247 u4E0A u7CFB u7EDFSOC u6E90 u4EE3 u7801 u5206 u6790 u7684SRAM u63A5 u53E3 u4EE3
SRAM
- SRAM读写测试实例，每秒钟进行一次单字节的SRAM 读和写操作，用chipscope查看时序波形。(SRAM read and write test instances, each time a single byte SRAM Read and write operations, use chipscope to see the timing waveform.)
ad_prj1.4.3
- AD采集固定点数FPGA对采集数据进行指定次数累加，存储至片外SRAM并等待上位机发送取数据指令(The AD acquisition fixed point number FPGA adds the number of data to the collected data, stores it to the outside SRAM and waits for the upper computer to send the data instruction)
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)