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74LS138
- 用VHDL 语言描述度三线八线译码器，其开发均在FPGA中-using VHDL descr iption line 8 3 degrees decoder lines, the development is in FPGA
yimaqi
- 7段译码器 将0，1，2，3，4，5，6，7，8，9翻译成数码管显示-7 decoder will be translated into digital 0,1,2,3,4,5,6,7,8,9 display
sxbxymq_t15
- 3线8线译码器vhdl实现的，很好用，希望初学者好好看看！-3 lines and 8 line decoder vhdl, good with beginners a good look!
vhdl
- 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
z138
- 译码电路设计，用VHDL语言设计一个3线-8线译码器的方法-Decoding circuit design using VHDL language to design a 3-to-8 line decoder method
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3