将256位数据宽度 通过两级FIFO 转成16位 使用XILINX的ISE10.1完成设计 此为工程文件 有仿真结果-The 256-bit data width conversion FIFO through the two 16-bit using the XILINX s ISE10.1 to complete the design documents for the works in this simulation results

这是一个在xilinx下运行的关于FIFO的IP核设计的程序。-This is a run on the FIFO xilinx IP core design process.

异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.