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5.8
- 还是一个verilog原代码,可以在modelsim下运行,强烈推荐下载-or a Verilog source code can be run in modelsim strongly recommend downloading
allidt_20020616.tar
- idt的双口ram的读写接口程序，verilog 代码，并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
Find_medium_value_co-design_of_C_and_Verilog
- A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
RGB_color_transform_gray_level_co-design_of_C_and_
- to use verilog code and c to translate a RGB bmp image(512*512) to a gray level image
show_your_student_ID_number_co-design_of_C_and_Ver
- As the source code name, this code is writing in Verilog and also inside the folder there is a c code to see the simulation results from verilog.