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verilog for uart
- 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver / transmitter (UART) can be programmed to control computer attached to the serial device interface microchips.
伪随机序列
- 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and ci
用verilog硬件描述语言编写的fft算法
- 用verilog硬件描述语言编写的fft算法，很是经典，和大家共享，希望能对大家有所帮助。,Verilog hardware descr iption language with the preparation of the fft algorithm, it is a classic, and we share the hope that it can be helpful to everyone.
Descrambler
- ofdm中相位检测的Verilog程序，很不错，可以在Xilinxfpga上运行。-phase detection in ofdm Verilog program, very good, you can Xilinxfpga run.
SDRAM50M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是50M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 50 m, the hope can help you
SDRAM100M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是100M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 100m, the hope can help you