此程序是用VHDL硬件描述语言编写的,实现四位全加器的功能-This procedure is used VHDL hardware descr iption languages, the realization of the four full-adder function

实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and

通过调用一位全加器模块,实现四位全加器功能-By calling a full adder module, four full adder function

实现四位全加器，为初学者提供参考说明，对VHDL语言有一定了解(it's a addler of four bits,which is designed for the new learner of VHDL language)