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fifoVerilog
- 设计一个异步FIFO,完成数据平滑功能,FIFO的深度为256,宽度为8位,实时给出读空和溢出指示,写时钟为带间隔的100MHz,读时钟为5MHz,代码为了便于读阅,存放在word文档,可直接拷贝到quartus或者ise编译平台下使用-Design an asynchronous FIFO, complete data smoothing function, the depth of the FIFO 256, and the width is 8 bits, real read empty
asyncfifo
- 异步fifo的设计,内含完整代码,亲测可用-Asynchronous fifo design, containing the complete code, pro-test available
FIFO Design
- 异步fifo设计经典文章,可作为异步fifo设计基础导读(Asynchronous FIFO design classic article, can be used as the basis for asynchronous FIFO Design Guide)
异步FIFO设计
- 经典的异步FIFO设计,First Input First Output的缩写,先入先出队列,这是一种传统的按序执行方法,先进入的指令先完成并引退,跟着才执行第二条指令。(Classic asynchronous FIFO design)