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FPGA-FIR-filter-design
- 用数字逻辑语言设计一个十六阶的FIR滤波器,通过数字电路实现滤波处理-Digital logic language design a sixteen-stage FIR filter, the filtering process is implemented by a digital circuit
FIR_GEN
- 书籍《数字信号处理的FPGA实现》中关于有限长单位冲激响应滤波器FIR的源代码。-Book Digital Signal Processing FPGA Implementation on the finite impulse response filter FIR units of source code.
基于FPGA和IP核的FIR低通滤波器
- 用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)