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基于VHDL的CPU程序
- 可实现加 减 与 或 非 移位功能的用vhdl语言编写可仿真的CPU程序
ADDER4B
- 此程序是用VHDL硬件描述语言编写的,实现四位全加器的功能-This procedure is used VHDL hardware descr iption languages, the realization of the four full-adder function
MFSK-VHDl
- MFSK调制程序，里面有仿真结果，VHDL语言编写，语言简单，易学易用。-MFSK modulation process, there are simulation results, VHDL language, language is simple, easy to learn and use.
vhdl
- 实现代码，A、B为输入、Y为输出，它们为8位向量。OE为输出使能，低电平有效。IE为输入锁存时能，上升沿有效。Ci为进位输入，Co为进位输出。 S0、S1、S2为运算逻辑选择输入： ，用vhdl语言编写，基于数字电路。-Implementation code, A, B input, Y the output, they are 8-bit vector. OE to output enable, active low. IE when the input latch, rising e
S2_div
- 这是用VHDL语言编写的一段分频程序，将一个频率等分-S2_div
booth
- 布斯公式求补码乘法的算法，用VHDL语言编写-booth algrithm, work out the 2 s complement mulitplier using VHDL
Alu
- 4位ALU逻辑运算器，用VHDL语言编写-4-bit ALU process using VHDL
UART
- 这是用VHDL语言编写的FPGA串口程序，希望对大家有用。-It is written in VHDL, FPGA serial program, we want to be useful.
GM
- 多路信号复用的基带发信系统的设计与建模 按照要求对选定的设计题目进行逻辑分析，画出实现电路原理图，设计出各模块电路的逻辑功能，编写VHDL语言程序，上机调试、仿真，记录实验结果波形，对实验结果进行分析；-Multiple baseband signals sent reuse system design and modeling in accordance with the requirements of the selected design topics logical analysis
Simple-clock
- 简单的时钟,用vhdl语言编写,具有暂停,复位的功能,-Simple clock, written in vhdl language, with a pause, reset,
80_MEM
- 次文档是一个用VHDL语言编写的小程序，对于VHDL语言的初学者来说很有指导意义~-Times a document is a VHDL language program, guiding significance for beginners VHDL language useful to
84_REG
- 这也是一个用VHDL语言编写的小代码，对于初学者应该会有帮助的-This is a small code using VHDL language for beginners should be helpful
deizuse
- 非阻塞赋值程序，用VHDL语言编写，方便初学者学习-Nonblocking assignment procedures, using VHDL language, easy for beginners to learn
liushuideng
- 用VHDL语言编写程序，在开发板cycloneii EP2C5T144C8N上显示流水灯。-VHDL language programming, the display lights on the water development board cycloneii EP2C5T144C8N.
JIJIA_XIUGAI1
- 用VHDL语言编写的出租车计价系统,系统较完善，有助于学生的VHDL课程设计-TAXI FEE SYSTEM
filter
- 此程序是一个用VHDL语言编写的fir滤波器。经过了仿真验证，很好用。-This procedure is a VHDL language fir filter. After the simulation, very good use.
hdb3codec
- 基于Quartus9开发的一个hdb3编码，译码的仿真程序，顶层用原理图，各个模块用VHDL语言编写！-Based on the development of a hdb3 Quartus9 coding, decoding simulation program, with top-level schematic, each module is written in VHDL language!
jiaotong
- 用VHDL语言编写的交通灯控制程序，亲自实现可用-Traffic lights control program written in VHDL language, personally implementation available
SVPWM
- 实现SVPWM的算法实现和仿真，基于FPGA平台用VHDL语言编写(Realization and Simulation of algorithm for realizing SVPWM)
数字时钟
- 基于VHDL语言编写的数字时钟程序，经验证，可以用硬件实现(Based on VHDL language digital clock program, verified, you can use hardware to achieve.)