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aaa3_8
- 基于quartus II软件 用verilog 语言描述的38译码器-quartus II verilog
38.58
- 基于VDHL的38译码器的实现与58分频器的实现 FPGA主芯片：CycloneII EP2C35F672C6-Based on VDHL decoder 38 with the divider 58 to achieve the main FPGA chip: CycloneII EP2C35F672C6
edashiyan
- eda实验，38译码器，7段显示，还有分频器的代码。-eda experiment, 38 decoders, 7-segment display, as well as crossovers code.
VHDL
- 一些简单基本的vhdl代码源程序，包扩三八译码器，数据选择器，30s倒计时器等-Some simple basic VHDL source code procedures, bag expanding 38 decoder, data selector, 30 s down timer, etc
decoder
- 三八译码器的程序设计，用于可编程逻辑实验三个开关控制八个灯的亮灭-Decoder 38 program designed for programmable logic control eight experimental three bright lights switch off
yimaqi
- 这是一个用Quter 2 编写的三八译码器-This is a written Quter 2 decoder 38
ym38
- 38译码器（74LS138）的Verilog的实现-38 decoder（74LS138） implementations Verilog