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MY
- 计数器和译码器的程序，基于EDA的VHDL语言-Counter and decoder procedures, based on the VHDL language EDA
EDA
- 基于MAX PLUS 2 FPGA 依据状态机结构的10禁止计数器 内附其仿真图-MAX PLUS 2 FPGA based state machine based on the structure of the 10 counter containing the prohibition of the simulation map
myeda
- eda的程序集，有1位全加器，移位寄存器，计数器，等等的设计-failed to translate
EDA
- EDA频率计数器十进制计数器，通信工程专业-EDApinivjishuqi
jishuqi
- EDA实现计数器功能十六进制和二十四进制-EDA counter function hex and 24 quaternary
Digital-system-EDA
- 四位二进制数可预置可逆计数器设计 学习使用MAX+PlusⅡ文本编辑器的模板输入方法,熟悉常用语句的语法现象，掌握VHDL功能描述和结构描述的方法。-Four binary number can be preset the reversible counter design learning using a text editor MAX+Plus Ⅱ template input method, familiar with common statement syntax phenomenon
ji-shu-qi
- 大学EDA实验做的关于计数器的实验报告，含有仿真结果，希望能帮助到大家。-homework help others
plj
- 使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6