本次设计是完成8bit的数据fifo传输，缓存为8个字节。包含读写功能，能正确实现功能，并通过时序仿真。- The design is complete fifo 8bit data transmission, the cache is 8 bytes. Contains read and write functions, can function properly implemented, and by timing simulation.

无加我哦哦我二节课我今儿看人家就是等你回家我就饿哦了解那就射了我儿我去盆里设立我了我了为理我了我二姐(No I oh oh I have two lessons today I see people are waiting for you to come home. I know it is hungry Oh my son shot me to set up my bowl for me my sister)

本文档提供了DSP对FPGA中的FIFO的读写时序以及编程思路，供大家参考。(This document provides DSP on the FPGA FIFO read and write timing and programming ideas for your reference.)