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verilogSerialcommunication
- FPGA实现RS-232串口收发的仿真过程(Quartus+Synplify+ModelSim)-On the RS-232 online asynchronous transceiver introduced a lot, recently there groping to do with the ModelSim timing simulation, combined with the online reference and their own thinking, do this thin
RS255-239_verilog_doc_matlab_essay
- RS(255,239) FEC , 编解码, FPGA, 《RS编解码的FPGA实现》, 东南大学硕士论文用到的源代码,以及详细讲解-RS(255,239), FEC, encoding and decoding, postgraduate s essay