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sheji2
- 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
RS_Verilog
- rs编解码的verilog实现源代码，从硬件实现rs的编解码-rs codec to achieve the verilog source code, from the hardware codec rs
RS(204.188)design
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
RS_coding_123
- RS编码的实现，包括C语言，C++，java，VHDL，DSP，matlab的RS编码实现，代码全部调是通过。-RS encoded, including the C language, C++, java, VHDL, DSPs, Matlab the RS coding, the code all the tune through.
RS
- 802.16d的RS编解码的VHDL实现-802.16d RS encoding and decoding in VHDL