搜索资源列表
M_design
- 设计一个简单的8比特ALU和一个简单的存储器，是用VerilogHDL实现的，这是个题目及其解析-Design of a simple 8-bit ALU and a simple memory, is used VerilogHDL realized, this is a subject and its analytic
ALU_design
- 设计一个简单的8比特ALU的源代码，是用VerilogHDL实现的-Design of a simple 8-bit ALU s source code is achieved using VerilogHDL
ALU---M_design
- 设计一个简单存储器的源代码，是用VerilogHDL实现的-Design of a simple memory of the source code, is used to achieve VerilogHDL
ISCASbenchmark
- ISCAS的benchmark 含有原理图，VHDL、VerilogHDL网表，测试数据等。 27-channel interrupt controller-ISCAS the benchmark contains schematic, VHDL, VerilogHDL netlist test data. 27-channel interrupt controller
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
ALU
- 用veriloghdl写的alu程序，对初学者会有帮助。-Writing with veriloghdl the alu procedures will be helpful for beginners.
vote_1
- 三人投票程序，用VerilogHDL写的，希望对大家有所帮助-Three of the voting procedure, with VerilogHDL Writing, and I hope to help everyone
crc
- 循环冗余校验码CRC的VerilogHDL源程序-CRC cyclic redundancy check code of the source VerilogHDL
VerilogHDL
- verilog 的很有用的教程 特别是对初学者会有很大的启发 希望对大家有用-verilog' s very useful especially for beginners course will be a source of inspiration to all of us hope that useful
SPI_Master(2byteperSPIcycle)
- 本人用VerilogHDL编写的SPI程序，该程序基于MAX3420E器件，一个SPI周期包括两个字节的传输，经测试，在MAX420E器件上功能正确，请放心使用！-I prepared SPI program MAX3420E-based devices, including a two-byte SPI cycle of transmission, by testing the device on MAX420E function correctly, please go!
VerilogHDL
- 这是学习Verilog的好的课件！！分享给大家，希望可以互相帮助。-It is good to learn Verilog courseware! ! We share the hope that you can help each other.
verilog_hdl_135
- veriloghdl教程135例是对初学者的引导，挺好的，要慢慢看-verilog hdl is a beginners tutorial 135 cases of guidance, in very good shape, it is necessary to wait and see
digi_clock
- VerilogHDL程序，功能是可以实现一个数字电子时钟。-It s a Verilog-HDL procedure which can makes a digital electronic clock.
simple_counter
- 改程序完成了计数功能，用到Veriloghdl编程实现，竟FPGA下载验证通过-To change the counting process is completed, use Veriloghdl programming, actually verified by FPGA Download
FFT
- 该源码是fft的Veriloghdl实现，通过FPGA下载验证通过，读者可以使用-The source is the fft of Veriloghdl achieved by FPGA download is validated, the reader can use
Verilog
- 该代码是Veriloghdl语言实现的串口通信，经过FPGA板子下载验证通过，读者可以使用-The code is Veriloghdl language of the serial communications, after verification by FPGA board download, readers can use
verilog232
- 该源码是关于Veriloghdl语言编写的rs232串口实现，通过下载得到验证-The source code is written in on the Veriloghdl rs232 serial interface, be verified by downloading
VerilogHDL
- 数字系统设计与VerilogHDL（第3版）教案-Digital System Design and VerilogHDL (version 3) lesson plans
VHDL学习资料
- VerilogHDL驱动喝程序设计以及实践的基础学习资料，有兴趣的可以看看(VerilogHDL learning data)
串口VerilogHDL
- 16倍率采样，带数字滤波，非自己原创，请勿用作商业用途(16 double rate sampling, digital filter, non original, do not use for commercial use)