搜索资源列表
tongbu
- 使用VERILOG开发时钟同步算法，能够从数据信号中提取时钟信息，-Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,
RS(204.188)design
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po
3-22
- verilog 中RLS算法的实现功能 已经在仿真窗口的波形实现-verilog about rls algorithm
CRC3
- CRC3算法 verilog 实现,循环校验，在传输数据时通过crc算法，验证数据是否传输正确-CRC3 algorithm verilog achieve, cyclic check whether the transmission data by the the crc algorithm, validation data transferred correctly
da_fir
- 基于verilog的分布式算法FIR滤波器 有两个文件 一个用来生成查找表-FIR filter using Distributed Algorithm.
cordic--sign
- cordic算法 计算三角函数 的verilog实现-the cordic algorithm computes trigonometric functions verilog implementation
Viterbi
- viterbi 译码相关算法讲解和Verilog代码，代码已经通过仿真验证没问题。-viterbi decoding algorithm explanation and Verilog code, the code has been verified by simulation problems.
AES-based-on-FPGA-jiemi
- 基于FPGA的AES算法实现，使用verilog语言实现。本模块只包含解密过程，没有加密过程。-Implementation of AES algorithm based on FPGA, using Verilog language. This module contains only the decryption process, no encryption process.
Canny
- 首先利用C实现了一个图像边缘提取的算法，然后利用vivado高层次综合，将其综合为verilog代码。-First, the use of C implements a image edge extraction algorithm, then use vivado high-level synthesis, as its comprehensive verilog code.
SEQ_MULT
- SEQUENTIAL MULTIPLIER IN VERILOG USING BOOTH S ALGORITHM
booth_multiplie_module
- 利用verilog实现的Booth算法乘法器，对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
AD_filter
- 一个最简单的verilog实现的ad采样数据滤波的算法。可以用来学习ad数据的滤波.-One of the simplest ad sampled data filtering algorithm verilog achieve. Learning can be used to filter data ad
control_s
- 数控机床 多轴插补原理积分算法，实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)
基于FPGA的高斯随机数发生器的设计与实现_徐新才
- 介绍了一种利用FPGA硬件平台生成高斯随机数的算法。(An algorithm for generating Gauss random numbers using FPGA hardware platform is introduced)
21ic下载_sm4算法_Verilog
- sm4加密算法fpga实现，采用verliog语言(SM4 encryption algorithm FPGA implementation, using verliog language)
SM3算法verilog实现
- SM3算法verilog实现,利用alter芯片开发的sm3算法实现(Implementation of SM3 algorithm Verilog and implementation of Sm3 algorithm developed by alter chip)
src
- 用verilog实现ldpc最小和译码算法(This code is for the decode of MS-algorithm based on LDPC.)
同步
- 基于FPGA的位同步算法的verilog实现(Verilog implementation of synchronization algorithm)
GCD
- 输入为两个32位数值，用辗转相减法实现的最大公约数算法进行输出，含有置位信号。(The input is two 32 bit values, and the algorithm of the greatest common divisor realized by the subtractive subtraction algorithm carries out the output, which contains the set signal.)
Verilog-Generator-of-Neural-Networks
- 利用DE0nano开发板实现了对用的卷积神经网络(The CNN algorithm is implemented.based FPGA)